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| CY7C1062AV25 512K x 32 Static RAM Features * High speed -- tAA = 10 ns * Low active power -- 745 mW (max.) * Operating voltages of 2.5 0.2V * 1.5V data retention * Automatic power-down when deselected * TTL-compatible inputs and outputs * Easy memory expansion with CE1, CE2, and CE3 features * Available in non Pb-free 119-ball pitch ball grid array package Functional Description The CY7C1062AV25 is a high-performance CMOS Static RAM organized as 524,288 words by 32 bits. Writing to the device is accomplished by enabling the chip (CE1, CE2 and CE3 LOW) and forcing the Write Enable (WE) input LOW. If Byte Enable A (BA) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A18). If Byte Enable B (BB) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A18). Likewise, BC and BD correspond with the I/O pins I/O16 to I/O23 and I/O24 to I/O31, respectively. Reading from the device is accomplished by enabling the chip (CE1, CE2, and CE3 LOW) while forcing the Output Enable (OE) LOW and Write Enable (WE) HIGH. If the first Byte Enable (BA) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte Enable B (BB) is LOW, then data from memory will appear on I/O8 to I/O15. Similarly, Bc and BD correspond to the third and fourth bytes. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O0 through I/O31) are placed in a high-impedance state when the device is deselected (CE1, CE2or CE3 HIGH), the outputs are disabled (OE HIGH), the byte selects are disabled (BA-D HIGH), or during a write operation (CE1, CE2, and CE3 LOW, and WE LOW). The CY7C1062AV25 is available in a 119-ball pitch ball grid array (PBGA) package. Logic Block Diagram INPUT BUFFERS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER 512K x 32 ARRAY OUTPUT BUFFERS SENSE AMPS WE CE1 CE2 CE3 OE BA BB BC BD I/O0-I/O31 COLUMN DECODER Cypress Semiconductor Corporation Document #: 38-05333 Rev. *A A 10 A 11 A 12 A 13 A 14 A 15 A 16 A 17 A 18 * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised July 10, 2006 [+] Feedback CONTROL LOGIC CY7C1062AV25 Selection Guide -10 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Com'l/Ind'l Com'l/Ind'l 10 275 50 Unit ns mA mA Pin Configuration 119-ball PBGA (Top View) 1 A B C D E F G H J K L M N P R T U I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 NC I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 2 A A Bc VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD A A A 3 A A CE2 VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS Bd A A 4 A CE1 NC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC WE OE 5 A A CE3 VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS Bb A A 6 A A Ba VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD A A A 7 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 DNU I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 Document #: 38-05333 Rev. *A Page 2 of 9 [+] Feedback CY7C1062AV25 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC Relative to GND [1] Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-up Current...................................................... >200 mA Operating Range Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 2.5V 0.2V .... -0.5V to +3.6V DC Voltage Applied to Outputs in High-Z State[1] ....................................-0.5V to VCC + 0.5V DC Input Voltage[1] .................................-0.5V to VCC + 0.5V DC Electrical Characteristics Over the Operating Range -10 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-down Current--TTL Inputs Automatic CE Power-down Current --CMOS Inputs GND < VI < VCC GND < VOUT < VCC, Output Disabled VCC = Max., f = fMAX = 1/tRC Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX Com'l/Ind'l Com'l/Ind'l Test Conditions VCC = Min., IOH = -1.0 mA VCC = Min., IOL = 1.0 mA 2.0 -0.3 -1 -1 Min. 2.0 0.4 VCC + 0.3 0.8 +1 +1 275 100 50 Max. Unit V V V V A A mA mA mA Max. VCC, CE > VCC - 0.2V, Com'l/Ind'l VIN > VCC - 0.2V, or VIN < 0.2V, f = 0 Capacitance[2] Parameter CIN COUT Description Input Capacitance I/O Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 2.5V Max. 8 10 Unit pF pF AC Test Loads and Waveforms[3] 50 OUTPUT Z0 = 50 VTH = VDD/2 30 pF Including all Components R1 317 of Test Equipment 2.3V 90% GND Rise time > 1 V/ns THEVENIN EQUIVALENT 167 OUTPUT 10% 90% 10% Fall time: > 1 V/ns ALL INPUT PULSES (a) 2.5V Including OUTPUT Jig and Scope 5 pF (b) R2 351 1.73V (c) Notes: 1. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 2. Tested initially and after any design or process changes that may affect these parameters. 3. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (2.3V). As soon as 1ms (Tpower) after reaching the minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 1.5V) voltage. Document #: 38-05333 Rev. *A Page 3 of 9 [+] Feedback CY7C1062AV25 AC Switching Characteristics Over the Operating Range[4] -10 Parameter Read Cycle tpower tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW Cycle[8, 9] Write Cycle Time CE1, CE2, or CE3 LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE HIGH to Low-Z[6] WE LOW to High-Z [6] Description VCC (typical) to the first access[5] Read Cycle Time Address to Data Valid Data Hold from Address Change CE1, CE2, or CE3 LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z [6] [6] Min. 1 10 Max. Unit ms ns 10 3 10 5 1 5 3 5 0 10 5 1 5 10 7 7 0 0 7 5.5 0 3 5 7 High-Z[6] Power-up[7] Power-down[7] ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns OE HIGH to High-Z CE1, CE2, or CE3 LOW to Low-Z[6] CE1, CE2, or CE3 HIGH to CE1, CE2, or CE3 LOW to CE1, CE2, or CE3 HIGH to Byte Enable to Data Valid Byte Enable to Byte Disable to Low-Z[6] High-Z[6] Byte Enable to End of Write Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.1V, input pulse levels of 0 to 2.3V, and output loading of the specified IOL/IOH and transmission line loads. Test conditions for the read cycle use output loading as shown in (a) of AC Test Loads, unless specified otherwise. 5. This part has a voltage regulator that steps down the voltage from 2.3V to 2V internally. tpower time has to be provided initially before a read/write operation is started. 6. tHZOE, tHZCE, tHZWE, tHZBE, and tLZOE, tLZCE, tLZWE, and tLZBE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 7. These parameters are guaranteed by design and are not tested. 8. The internal write time of the memory is defined by the overlap of CE1 LOW, CE 2 HIGH, CE3 LOW, and WE LOW. The chip enables must be active and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05333 Rev. *A Page 4 of 9 [+] Feedback CY7C1062AV25 Data Retention Waveform DATA RETENTION MODE VCC 2.3V tCDR CE VDR > 1.5V 2.3V tR Switching Waveforms Read Cycle No. 1[11,12] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[11,13] ADDRESS tRC CE1, CE3 CE2 tACE OE tDOE BA, BB, BC , BD tLZOE tDBE tLZBE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZCE tHZBE DATA VALID tPD 50% ISB IICC CC tHZOE HIGH IMPEDANCE DATA OUT Notes: 10. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 s or stable at VCC(min.) > 100 s 11. Device is continuously selected. OE, CE, BA, BB, BC, BD= VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW. Document #: 38-05333 Rev. *A Page 5 of 9 [+] Feedback CY7C1062AV25 Switching Waveforms Write Cycle No. 1 (CE Controlled)[14,15,16] tWC ADDRESS CE tSA tSCE tAW tPWE WE tBW BA, BB, BC , BD tSD DATAI/O tHD tHA Write Cycle No. 2 (BLE or BHE Controlled)[14,15,16] tWC ADDRESS tSA BA, BB, BC , BD tAW tBW tHA tPWE WE tSCE CE tSD DATAI/O tHD Notes: 14. CE indicates a combination of all three chip enables. When ACTIVE LOW, CE indicates the CE1, CE2 and CE3 are LOW. 15. Data I/O is high-impedance if OE or BA, BB, BC, BD = VIH. 16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05333 Rev. *A Page 6 of 9 [+] Feedback CY7C1062AV25 Switching Waveforms Write Cycle No. 3 (WE Controlled, OE LOW) tWC ADDRESS CE tSCE tAW tSA tPWE tHA WE tBW BA, BB, BC, BD tHZWE DATA I/O tLZWE tSD tHD Truth Table CE1 CE2 CE3 H L L L L L L L L L L L L H H L L L L L L L L L L L H L L L L L L L L L L L L OE X X L L L L L X X X X X H WE X X H H H H H L L L L L H BA X X L L H H H L L H H H X BB X X L H L H H L H L H H X Bc X X L H H L H L H H L H X BD X X L H H H L L H H H L X I/O0- I/O7 High-Z High-Z Data Out Data Out High-Z High-Z High-Z Data In Data In High-Z High-Z High-Z High-Z I/O8- I/O15 High-Z High-Z Data Out High-Z Data Out High-Z High-Z Data In High-Z Data In High-Z High-Z High-Z I/O16- I/O23 High-Z High-Z Data Out High-Z High-Z Data Out High-Z Data In High-Z High-Z Data In High-Z High-Z I/O24- I/O31 High-Z High-Z Data Out High-Z High-Z High-Z Data Out Data In High-Z High-Z High-Z Data In High-Z Mode Power Down Power Down Read All Bits Read Byte A Bits Only Read Byte B Bits Only Read Byte C Bits Only Read Byte D Bits Only Write All Bits Write Byte A Bits Only Write Byte B Bits Only Write Byte C Bits Only Write Byte D Bits Only Selected, Outputs Disabled Power (ISB) (ISB) (ICC) (ICC) (ICC) (ICC) (ICC) (ICC) (ICC) (ICC) (ICC) (ICC) (ICC) Document #: 38-05333 Rev. *A Page 7 of 9 [+] Feedback CY7C1062AV25 Ordering Information Speed (ns) 10 Ordering Code CY7C1062AV25-10BGC CY7C1062AV25-10BGI Package Diagram 51-85115 Package Type 119-ball Plastic Ball Grid Array (14 x 22 x 2.4 mm) Operating Range Commercial Industrial Package Diagram 119-ball PBGA (14 x 22 x 2.4 mm) (51-85115) 51-85115-*B All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05333 Rev. *A Page 8 of 9 [+] Feedback CY7C1062AV25 Document History Page Document Title: CY7C1062AV25 512K x 32 Static RAM Document Number: 38-05333 REV. ** *A ECN NO. 119626 493565 Issue Date 01/29/03 See ECN Orig. of Change DFP NXR New Data Sheet Converted from Preliminary to Final Removed -8 and -10 speed bins Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Updated the ordering information table Description of Change Document #: 38-05333 Rev. *A Page 9 of 9 [+] Feedback |
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